TET=Val_0x0, RT=Val_0x0, FIFOE=Val_0x0
FIFO Control Register
| FIFOE | FIFO Enable This bit enables/disables the Tx FIFOs and Rx FIFOs. Whenever the value of this bit is changed both the Tx FIFO and Rx FIFO controller portion of FIFOs is reset. 0 (Val_0x0): FIFO disabled 1 (Val_0x1): FIFO enabled |
| RFIFOR | Rx FIFO Reset This bit resets the control portion of the Rx FIFO and treats the FIFO as empty. This will also deassert the DMA Rx request and single signals. Note that this bit is self-clearing. 1 (Val_0x1): Rx FIFO reset |
| XFIFOR | Tx FIFO Reset This bit resets the control portion of the Tx FIFO and treats the FIFO as empty. This will also deassert the DMA Tx request and single signals. Note that this bit is self-clearing. 1 (Val_0x1): Tx FIFO reset |
| TET | Tx Empty Trigger This field is used to select the empty threshold level at which the THRE interrupts will be generated when the mode is active. It also determines when the DMA_TX_REQ signal will be asserted when in certain modes of operation. For details on DMA support, refer to Section UART Functional Description. 0 (Val_0x0): FIFO Empty 1 (Val_0x1): 2 characters in FIFO 2 (Val_0x2): FIFO 1/4 full 3 (Val_0x3): FIFO 1/2 full |
| RT | Rx Trigger This field is used to select the trigger level in the Rx FIFO at which the Received Data Available interrupt will be generated. In Auto Flow Control mode, it is used to determine when the RTS signal will be deasserted only when RTC flow-control trigger is disabled. It also determines when the DMA_RX_REQ signal will be asserted when in certain modes of operation. For details on DMA support, refer to Section UART Functional Description. 0 (Val_0x0): 1 character in FIFO 1 (Val_0x1): FIFO 1/4 full 2 (Val_0x2): FIFO 1/2 full 3 (Val_0x3): FIFO 2 characters till full |